; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool igc_opt
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2022-2024 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; UNSUPPORTED: llvm-17-plus
; RUN: igc_opt --typed-pointers %s -S -o - -igc-constant-coalescing -dce | FileCheck %s

target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f80:128:128-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a:64:64-f80:128:128-n8:16:32:64"

define <4 x float> @f0(i32 %src) {
;
; CHECK-LABEL: @f0(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = inttoptr i32 [[SRC:%.*]] to i8 addrspace(2490373)*
; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.genx.GenISA.ldrawvector.indexed.v16f32.p2490373i8(i8 addrspace(2490373)* [[TMP0]], i32 [[SRC]], i32 4, i1 false)
; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <16 x float> [[TMP1]], i32 12
; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <16 x float> [[TMP1]], i32 8
; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <16 x float> [[TMP1]], i32 4
; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <16 x float> [[TMP1]], i32 0
; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <4 x float> undef, float [[TMP5]], i32 0
; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x float> [[TMP6]], float [[TMP4]], i32 1
; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[TMP3]], i32 2
; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x float> [[TMP8]], float [[TMP2]], i32 3
; CHECK-NEXT:    ret <4 x float> [[TMP9]]
;
entry:
  %0 = inttoptr i32 %src to i8 addrspace(2490373)*
  %1 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %src, i32 4, i1 false)
  %2 = add i32 %src, 16
  %3 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %2, i32 4, i1 false)
  %4 = add i32 %src, 32
  %5 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %4, i32 4, i1 false)
  %6 = add i32 %src, 48
  %7 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %6, i32 4, i1 false)
  %8 = insertelement <4 x float> undef, float %1, i32 0
  %9 = insertelement <4 x float> %8, float %3, i32 1
  %10 = insertelement <4 x float> %9, float %5, i32 2
  %11 = insertelement <4 x float> %10, float %7, i32 3
  ret <4 x float> %11
}



define <4 x float> @f1(i32 %src) {
;
; CHECK-LABEL: @f1(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = inttoptr i32 [[SRC:%.*]] to i8 addrspace(2490373)*
; CHECK-NEXT:    [[TMP1:%.*]] = call <1 x float> @llvm.genx.GenISA.ldrawvector.indexed.v1f32.p2490373i8(i8 addrspace(2490373)* [[TMP0]], i32 [[SRC]], i32 4, i1 false)
; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <1 x float> [[TMP1]], i32 0
; CHECK-NEXT:    call void @llvm.genx.GenISA.storeraw.indexed.p2490373i8.f32(i8 addrspace(2490373)* [[TMP0]], i32 [[SRC]], float 0.000000e+00, i32 4, i1 false)
; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[SRC]], 4
; CHECK-NEXT:    [[TMP4:%.*]] = call <16 x float> @llvm.genx.GenISA.ldrawvector.indexed.v16f32.p2490373i8(i8 addrspace(2490373)* [[TMP0]], i32 [[TMP3]], i32 4, i1 false)
; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <16 x float> [[TMP4]], i32 11
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <16 x float> [[TMP4]], i32 7
; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <16 x float> [[TMP4]], i32 0
; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> undef, float [[TMP2]], i32 0
; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x float> [[TMP8]], float [[TMP7]], i32 1
; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x float> [[TMP9]], float [[TMP6]], i32 2
; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP5]], i32 3
; CHECK-NEXT:    ret <4 x float> [[TMP11]]
;
entry:
  %0 = inttoptr i32 %src to i8 addrspace(2490373)*
  %1 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %src, i32 4, i1 false)
  call void @llvm.genx.GenISA.storeraw.indexed.p2490373i8.f32(i8 addrspace(2490373)* %0, i32 %src, float 0x0, i32 4, i1 false)
  %2 = add i32 %src, 4
  %3 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %2, i32 4, i1 false)
  %4 = add i32 %src, 32
  %5 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %4, i32 4, i1 false)
  %6 = add i32 %src, 48
  %7 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %6, i32 4, i1 false)
  %8 = insertelement <4 x float> undef, float %1, i32 0
  %9 = insertelement <4 x float> %8, float %3, i32 1
  %10 = insertelement <4 x float> %9, float %5, i32 2
  %11 = insertelement <4 x float> %10, float %7, i32 3
  ret <4 x float> %11
}


define <4 x float> @f2(i32 %src) {
;
; CHECK-LABEL: @f2(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP0:%.*]] = inttoptr i32 [[SRC:%.*]] to i8 addrspace(2490373)*
; CHECK-NEXT:    [[TMP1:%.*]] = call <1 x float> @llvm.genx.GenISA.ldrawvector.indexed.v1f32.p2490373i8(i8 addrspace(2490373)* [[TMP0]], i32 [[SRC]], i32 4, i1 false)
; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <1 x float> [[TMP1]], i32 0
; CHECK-NEXT:    br label [[STOREBB:%.*]]
; CHECK:       storeBB:
; CHECK-NEXT:    call void @llvm.genx.GenISA.storeraw.indexed.p2490373i8.f32(i8 addrspace(2490373)* [[TMP0]], i32 [[SRC]], float 0.000000e+00, i32 4, i1 false)
; CHECK-NEXT:    br label [[EXITBB:%.*]]
; CHECK:       exitBB:
; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[SRC]], 4
; CHECK-NEXT:    [[TMP4:%.*]] = call <16 x float> @llvm.genx.GenISA.ldrawvector.indexed.v16f32.p2490373i8(i8 addrspace(2490373)* [[TMP0]], i32 [[TMP3]], i32 4, i1 false)
; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <16 x float> [[TMP4]], i32 11
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <16 x float> [[TMP4]], i32 7
; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <16 x float> [[TMP4]], i32 0
; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> undef, float [[TMP2]], i32 0
; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x float> [[TMP8]], float [[TMP7]], i32 1
; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x float> [[TMP9]], float [[TMP6]], i32 2
; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP5]], i32 3
; CHECK-NEXT:    ret <4 x float> [[TMP11]]
;
entry:
  %0 = inttoptr i32 %src to i8 addrspace(2490373)*
  %1 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %src, i32 4, i1 false)
  br label %storeBB
storeBB:
  call void @llvm.genx.GenISA.storeraw.indexed.p2490373i8.f32(i8 addrspace(2490373)* %0, i32 %src, float 0x0, i32 4, i1 false)
  br label %exitBB
exitBB:
  %2 = add i32 %src, 4
  %3 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %2, i32 4, i1 false)
  %4 = add i32 %src, 32
  %5 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %4, i32 4, i1 false)
  %6 = add i32 %src, 48
  %7 = call fast float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)* %0, i32 %6, i32 4, i1 false)
  %8 = insertelement <4 x float> undef, float %1, i32 0
  %9 = insertelement <4 x float> %8, float %3, i32 1
  %10 = insertelement <4 x float> %9, float %5, i32 2
  %11 = insertelement <4 x float> %10, float %7, i32 3
  ret <4 x float> %11
}



; Function Attrs: argmemonly nounwind readonly willreturn
declare float @llvm.genx.GenISA.ldraw.indexed.f32.p2490373i8(i8 addrspace(2490373)*, i32, i32, i1) argmemonly nounwind readonly willreturn

; Function Attrs: argmemonly nounwind writeonly
declare void @llvm.genx.GenISA.storeraw.indexed.p2490373i8.f32(i8 addrspace(2490373)*, i32, float, i32, i1) argmemonly nounwind writeonly


!igc.functions = !{!0, !3, !4}

!0 = !{<4 x float> (i32)* @f0, !1}
!3 = !{<4 x float> (i32)* @f1, !1}
!4 = !{<4 x float> (i32)* @f2, !1}

!1 = !{!2}
!2 = !{!"function_type", i32 0}

