;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2025 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================
; REQUIRES: llvm-14-plus, regkeys
;
; RUN: igc_opt --opaque-pointers -platformbmg -igc-emit-visa %s -regkey DumpVISAASMToConsole | FileCheck %s
; ------------------------------------------------
; EmitVISAPass
; ------------------------------------------------

; This test checks stack memory allocation for uniform and non-uniform
; vlaStackAlloca calls

; CHECK-LABEL: .kernel "test_uniform"
; CHECK: add (M1_NM, 1) SP(0,0)<1> privateBase(0,0)<0;1,0> {{.*}}(0,0)<0;1,0>
; CHECK: mov (M1_NM, 1) FP(0,0)<1> SP(0,0)<0;1,0>
; CHECK: mul (M1_NM, 1) vlaSize(0,0)<1> array_size(0,0)<0;1,0> 0x4:w
; CHECK: add (M1, 32) vlaStackAlloca(0,0)<1> SP(0,0)<0;1,0> 0x0:d
; CHECK: add (M1_NM, 1) SP(0,0)<1> SP(0,0)<0;1,0> vlaSize(0,0)<0;1,0>

define spir_kernel void @test_uniform(i32 %array_size, <8 x i32> %r0, <8 x i32> %payloadHeader, ptr %privateBase, i32 %bufferOffset, i16 %localIdX, i16 %localIdY, i16 %localIdZ) #0 {
entry:
  %vlaSize = mul i32 %array_size, 4
  %vlaStackAlloca = call ptr @llvm.genx.GenISA.VLAStackAlloca(i32 0, i32 %vlaSize)
  store i32 %array_size, ptr %vlaStackAlloca, align 4
  ret void
}

; CHECK-LABEL: .kernel "test_non_uniform"
; CHECK: add (M1_NM, 1) SP(0,0)<1> privateBase(0,0)<0;1,0> {{.*}}(0,0)<0;1,0>
; CHECK: mov (M1_NM, 1) FP(0,0)<1> SP(0,0)<0;1,0>
; CHECK: mov (M1_NM, 8) simdLaneId(0,0)<1> 0x76543210:v
; CHECK: add (M1_NM, 8) simdLaneId(0,8)<1> simdLaneId(0,0)<1;1,0> 0x8:w
; CHECK: add (M1_NM, 16) simdLaneId(0,16)<1> simdLaneId(0,0)<1;1,0> 0x10:w
; CHECK: mov (M1, 32) simdLaneIdExt(0,0)<1> simdLaneId_0v(0,0)<1;1,0>
; CHECK: mul (M1_NM, 1) vlaSize(0,0)<1> array_size(0,0)<0;1,0> 0x4:w
; CHECK: mul (M1, 32) vlaOffset(0,0)<1> vlaSize(0,0)<0;1,0> simdLaneIdExt(0,0)<1;1,0>
; CHECK: add (M1, 32) vlaStackAlloca(0,0)<1> SP(0,0)<0;1,0> vlaOffset(0,0)<1;1,0>
; CHECK: mul (M1_NM, 1) vlaSize_0v(0,0)<1> vlaSize(0,0)<0;1,0> 0x20:uw
; CHECK: add (M1_NM, 1) SP(0,0)<1> SP(0,0)<0;1,0> vlaSize_0v(0,0)<0;1,0>

define spir_kernel void @test_non_uniform(i32 %array_size, <8 x i32> %r0, <8 x i32> %payloadHeader, ptr %privateBase, i32 %bufferOffset, i16 %localIdX, i16 %localIdY, i16 %localIdZ) #0 {
entry:
  %simdLaneId = call i16 @llvm.genx.GenISA.simdLaneId()
  %simdLaneIdExt = zext i16 %simdLaneId to i32
  %vlaSize = mul i32 %array_size, 4
  %vlaOffset = mul i32 %vlaSize, %simdLaneIdExt
  %vlaStackAlloca = call ptr @llvm.genx.GenISA.VLAStackAlloca(i32 %vlaOffset, i32 %vlaSize)
  store i32 %array_size, ptr %vlaStackAlloca, align 4
  ret void
}


; CHECK-LABEL: .kernel "test_2x"
; CHECK: add (M1_NM, 1) SP(0,0)<1> privateBase(0,0)<0;1,0> {{.*}}(0,0)<0;1,0>          /// $9
; CHECK: mov (M1_NM, 1) FP(0,0)<1> SP(0,0)<0;1,0>                                     /// $10
; CHECK: mov (M1_NM, 8) simdLaneId(0,0)<1> 0x76543210:v                               /// $11
; CHECK: add (M1_NM, 8) simdLaneId(0,8)<1> simdLaneId(0,0)<1;1,0> 0x8:w               /// $12
; CHECK: add (M1_NM, 16) simdLaneId(0,16)<1> simdLaneId(0,0)<1;1,0> 0x10:w            /// $13
; CHECK: mov (M1, 32) simdLaneIdExt(0,0)<1> simdLaneId_0v(0,0)<1;1,0>                 /// $14
; CHECK: mul (M1_NM, 1) vlaSize(0,0)<1> array_size(0,0)<0;1,0> 0x4:w                  /// $15
; CHECK: mul (M1, 32) vlaOffset(0,0)<1> vlaSize(0,0)<0;1,0> simdLaneIdExt(0,0)<1;1,0> /// $16
; CHECK: add (M1, 32) vlaStackAlloca(0,0)<1> SP(0,0)<0;1,0> vlaOffset(0,0)<1;1,0>     /// $17
; CHECK: mul (M1_NM, 1) vlaSize_0v(0,0)<1> vlaSize(0,0)<0;1,0> 0x20:uw                /// $18
; CHECK: add (M1_NM, 1) SP(0,0)<1> SP(0,0)<0;1,0> vlaSize_0v(0,0)<0;1,0>              /// $19
; CHECK: add (M1, 32) vlaStackAlloca2(0,0)<1> SP(0,0)<0;1,0> 0x0:d                    /// $23
; CHECK: add (M1_NM, 1) SP(0,0)<1> SP(0,0)<0;1,0> vlaSize(0,0)<0;1,0>                 /// $24

define spir_kernel void @test_2x(i32 %array_size, <8 x i32> %r0, <8 x i32> %payloadHeader, ptr %privateBase, i32 %bufferOffset, i16 %localIdX, i16 %localIdY, i16 %localIdZ) #0 {
entry:
  %simdLaneId = call i16 @llvm.genx.GenISA.simdLaneId()
  %simdLaneIdExt = zext i16 %simdLaneId to i32
  %vlaSize = mul i32 %array_size, 4
  %vlaOffset = mul i32 %vlaSize, %simdLaneIdExt
  %vlaStackAlloca = call ptr @llvm.genx.GenISA.VLAStackAlloca(i32 %vlaOffset, i32 %vlaSize)
  store i32 %array_size, ptr %vlaStackAlloca, align 4
  %vlaStackAlloca2 = call ptr @llvm.genx.GenISA.VLAStackAlloca(i32 0, i32 %vlaSize)
  store i32 %array_size, ptr %vlaStackAlloca2, align 4
  ret void
}


declare i16 @llvm.genx.GenISA.simdLaneId()

declare ptr @llvm.genx.GenISA.VLAStackAlloca(i32, i32)

attributes #0 = { "hasVLA" }

!IGCMetadata = !{!0}
!igc.functions = !{!26, !34, !37}

!0 = !{!"ModuleMD", !1, !25}
!1 = !{!"FuncMD", !2, !3, !23, !24, !35, !36}
!2 = !{!"FuncMDMap[0]", ptr @test_uniform}
!3 = !{!"FuncMDValue[0]", !4, !19, !44}
!4 = !{!"resAllocMD", !5}
!5 = !{!"argAllocMDList", !6, !10, !11, !14, !15, !16, !17, !18}
!6 = !{!"argAllocMDListVec[0]", !7, !8, !9}
!7 = !{!"type", i32 0}
!8 = !{!"extensionType", i32 -1}
!9 = !{!"indexType", i32 -1}
!10 = !{!"argAllocMDListVec[1]", !7, !8, !9}
!11 = !{!"argAllocMDListVec[2]", !12, !8, !13}
!12 = !{!"type", i32 1}
!13 = !{!"indexType", i32 0}
!14 = !{!"argAllocMDListVec[3]", !7, !8, !9}
!15 = !{!"argAllocMDListVec[4]", !7, !8, !9}
!16 = !{!"argAllocMDListVec[5]", !7, !8, !9}
!17 = !{!"argAllocMDListVec[6]", !7, !8, !9}
!18 = !{!"argAllocMDListVec[7]", !7, !8, !9}
!19 = !{!"m_OpenCLArgTypeQualifiers", !20, !21, !22}
!20 = !{!"m_OpenCLArgTypeQualifiersVec[0]", !""}
!21 = !{!"m_OpenCLArgTypeQualifiersVec[1]", !""}
!22 = !{!"m_OpenCLArgTypeQualifiersVec[2]", !""}
!23 = !{!"FuncMDMap[1]", ptr @test_non_uniform}
!24 = !{!"FuncMDValue[1]", !4, !19, !51}
!25 = !{!"isHDCFastClearShader", i1 false}
!26 = !{ptr @test_uniform, !27}
!27 = !{!28}
!28 = !{!"function_type", i32 0}
!34 = !{ptr @test_non_uniform, !27}
!35 = !{!"FuncMDMap[2]", ptr @test_2x}
!36 = !{!"FuncMDValue[2]", !4, !19, !58}
!37 = !{ptr @test_2x, !27}
!38 = !{!"argId", i32 0}
!39 = !{!"implicitArgInfoListVec[0]", !38}
!40 = !{!"argId", i32 1}
!41 = !{!"implicitArgInfoListVec[1]", !40}
!42 = !{!"argId", i32 13}
!43 = !{!"implicitArgInfoListVec[2]", !42}
!44 = !{!"implicitArgInfoList", !39, !41, !43}
!45 = !{!"argId", i32 0}
!46 = !{!"implicitArgInfoListVec[0]", !45}
!47 = !{!"argId", i32 1}
!48 = !{!"implicitArgInfoListVec[1]", !47}
!49 = !{!"argId", i32 13}
!50 = !{!"implicitArgInfoListVec[2]", !49}
!51 = !{!"implicitArgInfoList", !46, !48, !50}
!52 = !{!"argId", i32 0}
!53 = !{!"implicitArgInfoListVec[0]", !52}
!54 = !{!"argId", i32 1}
!55 = !{!"implicitArgInfoListVec[1]", !54}
!56 = !{!"argId", i32 13}
!57 = !{!"implicitArgInfoListVec[2]", !56}
!58 = !{!"implicitArgInfoList", !53, !55, !57}
