;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2025 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; REQUIRES: llvm-14-plus
; RUN: igc_opt --typed-pointers --igc-scalar-arg-as-pointer-analysis -igc-serialize-metadata -S %s | FileCheck %s
;

; CHECK: !{!"m_OpenCLArgScalarAsPointersSet{{[[][0-9][]]}}", i32 5}
; CHECK: !{!"m_OpenCLArgScalarAsPointersSet{{[[][0-9][]]}}", i32 6}

%struct.__generated_KernelArgWithPtr = type { [2 x i8 addrspace(1)*], i32, i32 }
%struct.KernelArgWithPtr = type { [2 x i8 addrspace(4)*], i32, i32 }

; Function Attrs: convergent nounwind
define spir_kernel void @test(
%struct.__generated_KernelArgWithPtr* nocapture readonly byval(%struct.__generated_KernelArgWithPtr) align 8 %__arg_kArg, i64 %_arg_randIndex, <8 x i32> %r0, <3 x i32> %globalOffset, i8* %privateBase, i64 %const_reg_qword, i64 %const_reg_qword1, i32 %const_reg_dword, i32 %const_reg_dword2) #0 {
entry:
  %agg.tmp1 = alloca %struct.KernelArgWithPtr, align 8

  %0 = bitcast %struct.KernelArgWithPtr* %agg.tmp1 to i8*
  %__arg_kArg_alloca.sroa.0.0..sroa_cast = bitcast %struct.KernelArgWithPtr* %agg.tmp1 to i64*
  store i64 %const_reg_qword, i64* %__arg_kArg_alloca.sroa.0.0..sroa_cast, align 8
  %__arg_kArg_alloca.sroa.2.0..sroa_idx3 = getelementptr inbounds %struct.KernelArgWithPtr, %struct.KernelArgWithPtr* %agg.tmp1, i64 0, i32 0, i64 1
  %__arg_kArg_alloca.sroa.2.0..sroa_cast = bitcast i8 addrspace(4)** %__arg_kArg_alloca.sroa.2.0..sroa_idx3 to i64*
  store i64 %const_reg_qword1, i64* %__arg_kArg_alloca.sroa.2.0..sroa_cast, align 8
  %__arg_kArg_alloca.sroa.3.0..sroa_idx4 = getelementptr inbounds %struct.KernelArgWithPtr, %struct.KernelArgWithPtr* %agg.tmp1, i64 0, i32 1
  store i32 %const_reg_dword, i32* %__arg_kArg_alloca.sroa.3.0..sroa_idx4, align 8
  %__arg_kArg_alloca.sroa.4.0..sroa_idx5 = getelementptr inbounds %struct.KernelArgWithPtr, %struct.KernelArgWithPtr* %agg.tmp1, i64 0, i32 2
  store i32 %const_reg_dword2, i32* %__arg_kArg_alloca.sroa.4.0..sroa_idx5, align 4
  %add.i = add nsw i32 %const_reg_dword, %const_reg_dword2

  %bitCast = bitcast %struct.KernelArgWithPtr* %agg.tmp1 to i32 addrspace(4)**
  %arrayidx.i = getelementptr inbounds i32 addrspace(4)*, i32 addrspace(4)** %bitCast, i64 %_arg_randIndex

  %load = load i32 addrspace(4)*, i32 addrspace(4)** %arrayidx.i, align 8
  %arrayidx8.i = getelementptr inbounds i32, i32 addrspace(4)* %load, i64 5
  %spaceCast = addrspacecast i32 addrspace(4)* %arrayidx8.i to i32 addrspace(1)*
  store i32 15, i32 addrspace(1)* %spaceCast, align 4

  ret void
}

!igc.functions = !{!0}

!0 = !{void (%struct.__generated_KernelArgWithPtr*, i64, <8 x i32>, <3 x i32>, i8*, i64, i64, i32, i32)* @test, !1}
!1 = !{!2}
!2 = !{!"function_type", i32 0}
