Marsette Vona: Visolate Info

Marsette Vona: | Visolate Info

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## Introduction

Printed circuit boards are in virtually every piece of modern electronics. They typically start out as a sheet of fiberglass coated on one or both sides with copper. A photochemical process is normally used to remove much of that copper, leaving a pattern of traces to which electronic components are soldered forming the desired circuit.

For some applications, particularly very low-volume production in home or office environments or rapid-design cycle R&D, the setup costs, environmental hazards, and sensitivity of the chemical process suggest exploring other methods of PCB production. Mechanical etch is one alternative. This process also starts with a copper-clad PCB. However, the unwanted copper is removed mechanically rather than chemically. Most often, a fine-point rotary tool bit is used to create a separation in the copper around the boundary of each trace. The extra copper remaining between the traces is usually left in-place, as it is no longer electrically connected to any trace.

Here we explore an alternate method: compute the Voronoi region associated with each trace and cut along the boundaries between such regions. The image above shows the same printed circuit board (PCB) manufactured three different ways: by traditional photochemical process (right, this one has also been drilled and plated); by mechanical etch with standard outline toolpaths (middle); by mechanical etch with Voronoi toolpaths (left).

We developed a Java application, Visolate, which computes PCB isolation routing toolpaths, optionally following the boundaries of the entity Voronoi diagram induced by the traces. Given a board design, the program computes a toolpath for a CNC mill to cut out the traces.

Cutting the Voronoi boundaries has both advantages and disadvantages. Compared with boundary tracing, the Voronoi method produces only one cut instead of two to separate traces. This can produce cleaner and more consistent results for closely spaced traces. While there is no guarantee that the overall length of the Voronoi toolpath will be shorter than boundary tracing, in practice on real board designs we found that the Voronoi toolpath was on average nearly 40% shorter (see paper below). The Voronoi method usually produces "fat" traces, thus maximizing current carrying capacity, though in its basic form there is no way to specify particular traces that should be fattened more than others. On the downside, the Voronoi traces will have different second-order properties, such as parasitic capacitance, than the originally designed traces.

More information is available in a paper we wrote about the algorithms in our system: "Voronoi toolpaths for PCB mechanical etch: Simple and intuitive algorithms with the 3D GPU" by Marsette A. Vona and Daniela Rus, which is published in the proceedings of the International Conference on Robotics and Automation, 2005.

## Download

Visolate is released in precompiled source form under the GNU GPL.

## Status

This is highly experimental code. In particular, the gerber parser is incomplete (polygons and inverted images are not implemented, for example). We do not recommend driving any a CNC machine with g-code generated by Visolate unless you first carefully verify its safety.

## Requirements and Installation

Visolate has been tested under 1.5+ JREs from Sun with Java3D 1.5+ on GNU/Linux (Mozilla) and Windows (Firefox). Other JREs may work, but working installations of Java3D (not typically included with a JRE) and Swing (typically only included in full with Sun JREs, at the time of this writing) are required to run as a stand-alone application. Note that Java3D 1.5+ on Mac OS X itself apparrently requires JOGL.

## Acknowledgements

- The raster-to-vector algorithm is heavily inspired by Peter Selinger's potrace and his writeup Potrace: a polygon-based tracing algorithm.
- The voronoi computation is based on the following paper: Kenneth E. Hoff III, Tim Culver, John Keyser, Ming Lin, Dinesh Manocha. Fast Computation of Generalized Voronoi Diagrams Using Graphics Hardware. 1999.
- I learned some undocumented details of the gerber format from the source code for C. Scott Ananian's PCBMill Web Utilities and also the gerbv source code.

## Disclaimer

THIS INFORMATION AND/OR SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS INFORMATION AND/OR SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

vona@mit.edu | © 2008 Marsette Vona | Sun Sep 14 20:29:08 EDT 2008