commit b123e0d3345554d7e93361bb4511a53bc95d41a1
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Mon Aug 25 23:59:42 2014 +0200

    util/inteltool: fix typo
    
    Change-Id: I8c30742f6cd759dce4c9641edad107d9e3154975
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/6766
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ef3a17bd88f3c751ef98d3be94eb922da14ce3c5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 2 10:15:44 2014 +1000

    util/inteltool: Typo in dump output for 'GP_IO_SEL3'
    
    The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header
    is incorrectly reported as 'GPIO_SEL3'.
    
    Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6459
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 601da481b5437c7a73f97a1bece5990a393037d8
Author: Damien Zammit <damien@zamaudio.com>
Date:   Mon May 26 23:00:23 2014 +1000

    util/inteltool: Add pci ids for 4 northbridge models instead of 1.
    
    This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core.
    Tested on 0x0150 (0x0154 previously only model).
    
    Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Reviewed-on: http://review.coreboot.org/5873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ba1f9aaa9e05b40b55235dbe981880f9aa5c5136
Author: Lubomir Rintel <lkundrak@v3.sk>
Date:   Tue Jan 28 16:52:48 2014 +0000

    utils: Install man pages as non-executable (chmod 644)
    
    This bothers rpmlint.
    
    Change-Id: I27d9cfac3ef6834ff87acc5a5ccbf332e59eeb1a
    Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
    Reviewed-on: http://review.coreboot.org/5075
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit dcea700762bc97bd7fcabf2e960d47805129aeb1
Author: Damien Zammit <damien@zamaudio.com>
Date:   Wed Jul 17 23:59:40 2013 +1000

    inteltool: Print raw CPUID and make hexadecimal values unambiguous
    
    The raw CPUID is useful for matching the directories under 'src/cpu/intel'
    and is not easy to find out otherwise because it is most often decoded
    already. The decoded values are not obviously hexadecimal so prepend
    them with 0x to make sure they are unambiguous.
    
    The output differences look like this:
    -	CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
    +	CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2
    
    Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3788
    Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
    Tested-by: build bot (Jenkins)

commit dbc6fcd021759280c71b0e246c0ede34f4879bac
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Thu Jun 20 18:05:06 2013 +0200

    inteltool: add initial support for Nehalem
    
    Also, add pretty printing of Westmere's DMI registers (tested on my t410s
    by staring at non-zero output values :)
    
    Apparently Nehalem does not have a MEMBAR? But there are some
    documented memory controller control registers in PCI configuration
    space... left out for now.
    
    The PCIEXBAR is not documented publicly AFAICT, but there is
    a similar register on a device on bus 0xFF. phcoder might know more...
    
    Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3505
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 088f5694009f710dc0a7fc9437a02d05b08829ed
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Tue May 28 11:30:25 2013 +0200

    util/inteltool: Add support for other 5 chipsets
    
    e4e8e090fa36cb3a098e1ddf0ea44c796c140572 does add support for QM57,
    but there are many more that should work with that code(?).
    
    Does not explode on...
    CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
    Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor)
    Southbridge: 8086:3b0f (QS57)
    
    Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3321
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit e4e8e090fa36cb3a098e1ddf0ea44c796c140572
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Mar 31 13:51:37 2013 +0200

    util/inteltool: Add support for mobile 5 chipset
    
    Dump registers on mobile 5. Successfully tested on X201.
    
    Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/2993
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 17c05f23e215ff741bfc3fa611d7d2087198c3c1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Apr 3 10:00:33 2013 +0200

    inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflow
    
    When building inteltool with Clang, it warns about the following.
    
        $ clang --version
        Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
        Target: i386-pc-linux-gnu
        Thread model: posix
        $ CC=clang make
        […]
        clang -O2 -g -Wall -W   -c -o pcie.o pcie.c
        pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                        pciexbar_phys = pciexbar_reg & (0xff << 28);
                                                        ~~~~ ^  ~~
        pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                        pciexbar_phys = pciexbar_reg & (0x1ff << 27);
                                                        ~~~~~ ^  ~~
        pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                        pciexbar_phys = pciexbar_reg & (0x3ff << 26);
                                                        ~~~~~ ^  ~~
        3 warnings generated.
        […]
    
    Specifying the length by using the suffix `0xffULL` fixes these issues
    as now enough bits are available.
    
    These issues were introduced in commit 1162f25a [1].
    
        commit 1162f25a49e8f39822123d664cda10fef466b351
        Author: Stefan Reinauer <stepan@coresystems.de>
        Date:   Thu Dec 4 15:18:20 2008 +0000
    
            Patch to util/inteltool:
            * PMBASE dumping now knows the registers.
            * Add support for i965, i975, ICH8M
            * Add support for Darwin OS using DirectIO
    
    [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39822123d664cda10fef466b351
    
    Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3015
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 15a1fd1db9dd93004f808badcb15ca635177def6
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Apr 14 13:00:22 2013 +0200

    inteltool: Use portable type `uint64_t` instead of `u64`
    
    In [1] Idwer Vollering noted, that the type `u64` is not portable so
    on his FreeBSD system, the following warning is shown.
    
        $ clang -O2 -Wall -W -I/usr/local/include   -c -o amb.o amb.c
        amb.c:441:22: error: use of undeclared identifier 'u64'
                        ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) |
    
    The type `uint64_t` seems to be defined also on FreeBSD, so using this
    fixes the warning.
    
    Note, this warning is not reproducable with Debian Sid/unstable for
    example. I have no idea why though.
    
    [1] http://review.coreboot.org/#/c/3015/
    
    Change-Id: Ic22f4371114b68ae8221d84a01fef6888d43f365
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3086
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0c8b7d1ac272d5578e61c260a14f4fabbf3f53eb
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Apr 5 20:38:08 2013 +0200

    inteltool: remove unused file descriptor variable and ifdefs
    
    Change-Id: I6a119b1f362f481914377e8d14c713159f895130
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3030
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0dc775e894a3a7b3539eeeb4210bf8b796062274
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Apr 5 01:15:04 2013 +0200

    inteltool: use inttypes for prints in memory.c
    
    This fixes at least one warning on my machine where "llx" is replaced by PRIx64.
    
    Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3024
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5f3754e66dbe3b04c71c19fb106a92b30d475ab4
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Apr 5 00:12:21 2013 +0200

    inteltool: cpu.c: Use conversion specifier `u` for unsigned integers
    
    Cppcheck [1], a static code analysis tool, warns about the
    following.
    
        $ cppcheck --version
        Cppcheck 1.59
        $ cppcheck --enable=all .
        […]
        Checking cpu.c...
        [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
        [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
        […]
    
    And indeed, `core` is an unsigned integer and `man 3 printf` tells
    the following about conversion specifiers.
    
           d, i   The int argument is converted to signed decimal notation. […]
    
           o, u, x, X
                  The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or  unsigned  hexadecimal  (x  and  X)
                  notation.
    
    So use `u` and Cppcheck does not complain anymore.
    
    [1] http://cppcheck.sourceforge.net/
    
    Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3026
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3402a7fa7001e40035b6ae303b2e47b6281fef1c
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Apr 1 18:26:58 2013 +0200

    inteltool: Cast to `intptr_t` instead of `uint64_t`
    
    When building inteltool under x86-32, the following warnings are
    shown.
    
        $ gcc --version
        gcc-4.7.real (Debian 4.7.2-15) 4.7.2
        Copyright (C) 2012 Free Software Foundation, Inc.
        This is free software; see the source for copying conditions.  There is NO
        warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
        $ make
        […]
        amb.c: In function ‘amb_read_config32’:
        amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config16’:
        amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config8’:
        amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        […]
    
    Nico Huber commented the following [1].
    
        I don't see those warnings because I build for x86-64. I guess
        they could be fixed by casting to `ptrdiff_t` (from stddef.h)
        instead of `uint64_t`.
    
    And indeed, using `ptrdiff_t` fixes the warning. But as Stefan
    Reinauer commented in [2], `intptr_t` is more appropriate as this
    is just a pointer and no pointer difference.
    
    So `intptr_t` is taken, which fixes these issues warned about too.
    
    These warnings were introduced in commit »inteltool: Add support for
    dumping AMB registers« (4b7b320f) [3].
    
    [1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG
    [2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c
    [3] http://review.coreboot.org/525
    
    Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit a8db717d4af799fabd26383e6a748de94318d280
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 31 22:02:16 2013 +0200

    inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`
    
    When buidling inteltool with GCC, the following warning is printed.
    
        $ make
        […]
        gcc -O2 -g -Wall -W   -c -o memory.o memory.c
        memory.c: In function ‘print_mchbar’:
        memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat]
        […]
    
    This was introduced in commit »inteltool: Add support for H65 Express
    chipset« (c7fc4422) [1].
    
    Address this warning, by using `%llx` instead of `%lx`.
    
    [1] http://review.coreboot.org/1258
    
    Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2994
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9ebd8ea7cfd379cca56a2c48324bdfbe52ff6bab
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 31 22:15:43 2013 +0200

    inteltool: Allow to override Makefile variables
    
    Allow to override the variables `CC`, `INSTALL`, `PREFIX`,
    `CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`.
    
    This way for example a different compiler can easily be used.
    
        CC=clang make
    
    As a side note, Clang in contrast to GCC does *not* issue the
    following warnings.
    
        $ clang --version
        Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
        Target: i386-pc-linux-gnu
        Thread model: posix
        $ gcc --version
        gcc-4.7.real (Debian 4.7.2-15) 4.7.2
        Copyright (C) 2012 Free Software Foundation, Inc.
        This is free software; see the source for copying conditions.  There is NO
        warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
        $ make
        […]
        amb.c: In function ‘amb_read_config32’:
        amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config16’:
        amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config8’:
        amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        […]
    
    These are only shown under 32-bit and not 64-bit
    
        $ uname -m
        i686
    
    and are going to be fixed in a separate patch.
    
    Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2996
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 42c5501c3941ce0ddfc14bcd5b9d02d73d4f4e30
Author: Nico Huber <nico.h@gmx.de>
Date:   Mon Apr 1 15:38:44 2013 +0200

    inteltool: Add Cougar/Panther Point GPIO defaults
    
    This adds default values for the GPIO setup on Intel's Cougar Point and
    Panther Point platform controller hubs (PCH). Values are taken from [1] and
    [2], respectively. I've tested this with an H77 PCH. See below for the
    output.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    $ ./inteltool -G
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ========== GPIO DIFFS ===========
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    
    $ ./inteltool -gG
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ============= GPIOS =============
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    gpiobase+0x0008: 0x00000000 (RESERVED)
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    gpiobase+0x0010: 0x00000000 (RESERVED)
    gpiobase+0x0014: 0x00000000 (RESERVED)
    gpiobase+0x0018: 0x00040000 (GPO_BLINK)
    gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
    gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
    gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
    gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
    gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    gpiobase+0x003c: 0x00000000 (RESERVED)
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    gpiobase+0x004c: 0x00000000 (RESERVED)
    gpiobase+0x0050: 0x00000000 (RESERVED)
    gpiobase+0x0054: 0x00000000 (RESERVED)
    gpiobase+0x0058: 0x00000000 (RESERVED)
    gpiobase+0x005c: 0x00000000 (RESERVED)
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
    gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
    gpiobase+0x006c: 0x00000000 (RESERVED)
    gpiobase+0x0070: 0x00000000 (RESERVED)
    gpiobase+0x0074: 0x00000000 (RESERVED)
    gpiobase+0x0078: 0x00000000 (RESERVED)
    gpiobase+0x007c: 0x00000000 (RESERVED)
    
    Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3001
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 09dcbf0cdbae2e9a2b26f6753c290d8c70749bba
Author: Nico Huber <nico.h@gmx.de>
Date:   Mon Apr 1 15:08:04 2013 +0200

    inteltool: Add option to show differences in GPIO setup
    
    This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
    that differ from platform defaults. For differing registers, the current,
    the default, and an xor of the default and the current value is printed. A
    follow-up commit will add defaults for the Cougar/Panther Point platform
    controller hubs. If you specify both, -g and -G on the command line, all
    GPIO registers will be printed interleaved with the diff.
    
    Here's a preview:
    
    $ ./inteltool -G
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ========== GPIO DIFFS ===========
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    
    $ ./inteltool -gG
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ============= GPIOS =============
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    gpiobase+0x0008: 0x00000000 (RESERVED)
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    gpiobase+0x0010: 0x00000000 (RESERVED)
    gpiobase+0x0014: 0x00000000 (RESERVED)
    gpiobase+0x0018: 0x00040000 (GPO_BLINK)
    gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
    gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
    gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
    gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
    gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    gpiobase+0x003c: 0x00000000 (RESERVED)
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    gpiobase+0x004c: 0x00000000 (RESERVED)
    gpiobase+0x0050: 0x00000000 (RESERVED)
    gpiobase+0x0054: 0x00000000 (RESERVED)
    gpiobase+0x0058: 0x00000000 (RESERVED)
    gpiobase+0x005c: 0x00000000 (RESERVED)
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
    gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
    gpiobase+0x006c: 0x00000000 (RESERVED)
    gpiobase+0x0070: 0x00000000 (RESERVED)
    gpiobase+0x0074: 0x00000000 (RESERVED)
    gpiobase+0x0078: 0x00000000 (RESERVED)
    gpiobase+0x007c: 0x00000000 (RESERVED)
    
    Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3000
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5ed986b8ab6bbcf1dfcb7d43ab9d9c8c4bf2f60f
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 19:00:37 2013 +0100

    inteltool: Support PM registers on Cougar/Panther Point
    
    This adds the power management register definitions for Intel's Cougar
    Point and Panther Point platform controller hubs (PCH). The definitions
    are actually a subset of the older ICH10R registers: I've added just
    those that are mentioned in the public specifications in [1] and [2].
    I've tested dumping with an H77 PCH.
    
    NM70 is missing in [1]. Therefore, I didn't add it here.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2985
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 14290b3cbb4428cc6416d087433e9be09605ab17
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 19:08:39 2013 +0100

    inteltool: Add Cougar/Panther Point IDs to rootcmplx.c
    
    This adds the PCI IDs of Intel's Cougar Point and Panther Point platform
    controller hubs (PCH) to the dumping of the root complex configuration
    under the root complex base address (RCBA). Those PCHs are handled exactly
    as the older ICHs which can be seen in [1] and [2]. I've tested dumping
    with an H77 PCH.
    
    NM70 is missing in [1]. Therefore, I didn't add it here.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    Change-Id: I2296caae57e614171300362d41715deecec77762
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2986
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6983a6829ab20f31f351f39e6421710935c6a744
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 18:08:13 2013 +0100

    inteltool: Support GPIO registers on Cougar/Panther Point
    
    This adds the GPIO register definitions for Intel's Cougar Point and
    Panther Point platform controller hubs (PCH). All information is taken
    from the public specifications in [1] and [2]. I've tested it with an
    H77 PCH.
    
    NM70 is missing in [1]. Therefore, I didn't add it here.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2961
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 76d60494ef97399d4233f398be5814574f1d4a1b
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 17:57:15 2013 +0100

    inteltool: Add definitions for Cougar/Panther Point PCI IDs
    
    This adds correspondings #defines for the PCI IDs of the LPC device on
    Intel's Cougar Point and Panther Point platform controller hubs. Those
    will be used more in later commits.
    
    I've checked all those IDs against the specification updates [1] and [2].
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset Specification
        Update
        Document-Number: 324646-019
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
        Family - Datasheet Specification Update
        Document-Number: 326777-010
    
    Change-Id: Ibef5a30d283c568c345eb8d8149723e7a3049272
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2960
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 70f39871a92c065ee52be9d25aaf7a3e874fc1a3
Author: Olivier Langlois <olivier@olivierlanglois.net>
Date:   Fri Jan 25 00:49:46 2013 -0500

    inteltool: Add support for Atom N455 (0x106c0) in CPU MSRs dump
    
    reference for Atom MSRs are from
    Intel 64 and IA-32 Architectures Software Developer's Manual
    Volume 3C: System Programming Guide, Part 3
    Order Number 326019, January 2013, Table 35-4, 35-5
    
    Has been successfully tested on the targeted cpu.
    
    Change-Id: If94279caeab27121c63ec43c258dc962c167ad51
    Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2192
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit aa5eae629f40f4337f68b516f67c5c783ab65495
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Sep 24 10:58:41 2012 +0200

    inteltool: Add output of 64bit registers in PMBASE
    
    Output values of 64bit registers and fix settings for GPE0_EN for
    ICH9/10.
    
    Change-Id: I8ca6b32500331707670972b38466345f581844cd
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1625
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit fba86bfaa8a308ed6ca3daa66e27f1c10dd4c016
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Oct 12 10:36:49 2012 +0200

    inteltool: improve the libpci test in the Makefile
    
    Use the verbatim variable method to define and export test code and
    the actual libpci test from flashrom. This improves readability and
    will work with stricter compiler (settings).
    
    Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1575
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1a00cf063273d2f19afbc848dd1a204b7687578e
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sat Oct 13 06:23:52 2012 +0200

    inteltool: add support for 946GZ and 946PL
    
    Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 04c06005eb891e98fc733e85f625e13a16a86860
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sat Oct 13 02:19:30 2012 +0200

    inteltool: new definitions and cleanup
    
     - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
     - Refine some names and macros.
     - Clean up some whitespace errors.
    
     - Add IDs and names of 5, 6 and 7 Series southbridges and the three
       latest Core CPU families with integrated memory controllers but do
       not implement any pretty printing routines for them yet.
    
       The first generation Core family is already supported, although it
       was wrongly named after the PCH and used the wrong ID. Also, the BAR
       values have been mangled to 32b instead of 64b. Both errors have been
       fixed and most basic support for the other two generations was added.
    
    Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1574
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit f450b8619ebcd8dee94d175b2710f07e9884696d
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sat Oct 13 02:33:35 2012 +0200

    inteltool: remove bashism from Makefile
    
    &> is a bashism to redirect both outward streams (stdout and stderr), but
    with other shells this introduces a race condition with the rm command
    after it, because the compiler execution is done in the background/
    in parallel. Found and tested with dash.
    
    Change-Id: I08516494828c9f7af168f954f2df027372657867
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit c7fc4422a0039b6fd6c44bd98050ec648ee0312a
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Sat Jul 21 06:36:47 2012 +0400

    inteltool: Add support for H65 Express chipset
    
    Added few MCH and DMI registers for H65E.
    Description of them can be found at
    "2nd Generation Intel Core Processors
    Family datasheet"
    
    Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1258
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 56dfc7c6843f22d4491bc8b79a2afca72dd40e60
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jul 5 22:53:57 2012 +0200

    inteltool: fixup intel 5000 chipset pci ids
    
    Change-Id: I2cd1dac0dd9a5da1000a3ffa3e1c8ee4c5c8ba43
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1175
    Tested-by: build bot (Jenkins)

commit a7b296d450c5d948b95c1342f726334b4e5a4c68
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Nov 14 12:40:34 2011 -0800

    Fix warnings in coreboot utilities.
    
    - Fix some poor programming practice (breaks of strict aliasing as well
      as not checking the return value of read)
    - Use PRIx64 instead of %llx to prevent compilation warnings with both
      32bit and 64bit compilers
    - Use same compiler command options when linking inteltool and when
      detecting libpci for inteltool
    
    Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/752
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 4b7b320ff80c1047503e26fd387ba3d8acd996d9
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jan 8 15:27:18 2012 +0100

    inteltool: Add support for dumping AMB registers
    
    Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/525
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 54a5aedec69bac62bf9bb5f65e431130507235fb
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 30 13:30:36 2011 +0100

    inteltool: Add Intel i63xx I/O Controller Hub
    
    Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/356
    Tested-by: build bot (Jenkins)

commit 9beb5df3c4c35ddefa35742633a7876852065fae
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Mon Jun 27 14:35:00 2011 +0200

    inteltool: fixed 64 bit build
    
    The inline assembly for cpuid() was 32 bit specific. Additionally a
    format string referencing a size_t argument wasn't using the %z length
    modifier.
    
    Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/211
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 5782fee0e14557963149c47ad07cf1d235196f67
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Wed Mar 9 11:30:55 2011 +0100

    inteltool: Fixed building of position independent executables
    
    When building a position independent executable (PIE) EBX is used
    internally by the compiler to generate position independent address
    references so it cannot be used in the clobber list. Use the already
    existing code for the Darwin plattform for that case, too -- it'll
    preserve the EBX value.
    
    Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/209
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit bb41f502444b2d0295809cc882b829d768962990
Author: Ruud Schramp <schramp@holmes.nl>
Date:   Mon Apr 4 07:53:19 2011 +0200

    inteltool: added more device IDs
    
    Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
    Signed-off-by: Ruud Schramp <schramp@holmes.nl>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/185
    Tested-by: build bot (Jenkins)

commit 4cf7879cf032fca11d14bda68ba250931acd3e62
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 18 22:53:38 2011 +0000

    oops, one URL fix was missing. Add new DirectHW URL
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cff573d3a455c20d427e70db84fd2acfe59194d1
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 18 22:08:39 2011 +0000

    DirectHW fixes for coreboot utilities
    
    See http://www.coreboot.org/DirectHW for more information
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 312fc96874ff2b3fd1a839b72dd10edb1b8937b8
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Dec 17 22:34:58 2010 +0000

    inteltool: Model 0xf2x, ICH5, i865 support.
    
    Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
    registers on ICH5. Add ICH5 and i865 to the supported chips list.
    Enable the dumping of BAR6 on i865.
    
    Sample output:
    
      Disabling memory access:
      $ sudo setpci -s 6.0 0x04.b=0x0
    
      $ sudo ./inteltool -m | head -n 9
      Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7
      Intel Northbridge: 8086:2570 (i865)
      Intel Southbridge: 8086:24d0 (ICH5)
    
      ============= MCHBAR ============
    
      Access to BAR6 is currently disabled, attempting to enable.
      Enabled successfully.
      BAR6 = 0xfecf0000 (MEM)
    
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3645e61608a802f66b3109a090a591d9f2bb1dcd
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sat Nov 27 14:44:19 2010 +0000

    - Add support for Intel Pentium III MSRs
    - pmbase is on southbridge function 3 on I82371XX
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f91d813efe80045e322f7c6a767b403911b8a1c
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sun Oct 24 13:50:13 2010 +0000

    Add inteltool support for FreeBSD.
    
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Acked-by Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3cf287dab0d71cc7bfa864609016c47f3310a9e3
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:36:37 2010 +0000

    Add support for dumping ACPI registers for i7
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3d3cedf8021f1053788babacd629fd9eb1c988f
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:33:50 2010 +0000

    Add support for dumping RCBA registers for i7
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5329195e60ef26ce19562514671582040b5d32de
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:32:17 2010 +0000

    Remove some errant spaces
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3235eea7289ab274d74052613b2cd55732565310
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:31:13 2010 +0000

    Add DMIBAR support for Intel X58 southbridge
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7f2b0e339a2a051d5e0269eaa8fbb84530b6058
Author: Warren Turkal <wt@penguintechs.org>
Date:   Wed Sep 1 03:40:57 2010 +0000

    Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f366ce05ef3eb95c6c9d84a97cde1a4026f22787
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Tue Aug 17 08:33:44 2010 +0000

    Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
    Both are tested and appear to be working, however I'm not 100% clear
    on if the NM10 has any other PCI IDs.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d33dc40965c6f7f3dae585a330c2cd06b816c85
Author: Björn Busse <bj.rn@co-assembler.net>
Date:   Sun Aug 1 15:33:30 2010 +0000

    add i945GSE to inteltool
    
    Signed-off-by: Björn Busse <bj.rn@co-assembler.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23d98c768f0c0d53a71f77dd5f0ee83f01d66e16
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Jul 29 19:25:31 2010 +0000

    Add support for the Intel Atom D400/500- and N400-series integrated
    northbridge. Also add support for the very similar Q963/965 northbridge.
    Tested:
      D510: confirmed working, with MCHBAR enable code
      Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
    
    Untested:
      D410/D525/N400: should be the same northbridge
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e10757ed525cdd1a5263b9d79e284310c999c0f7
Author: Joseph Smith <joe@settoplinux.org>
Date:   Wed Jun 16 22:21:19 2010 +0000

    This patch adds inteltool support for i810E and ICH2.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74cd569821f2bc4148e1fb6281c587323d14811e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 1 10:04:28 2010 +0000

    inteltool: basic poulsbo sch support.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c60c88679f692dee5e547e58b4124c8639d4f07
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 30 12:35:39 2010 +0000

    whitespace cleanup inteltool cpu.c
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da0b456ad087daa384d30498132e4e59fa311e14
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Sun May 30 12:33:12 2010 +0000

    Added support to ICH9 chipset family
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14e22779625de673569c7b950ecc2753fb915b31
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 27 06:56:47 2010 +0000

    Since some people disapprove of white space cleanups mixed in regular commits
    while others dislike them being extra commits, let's clean them up once and
    for all for the existing code. If it's ugly, let it only be ugly once :-)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca3548e79fd9005d9e9a5694b438bedd87e70560
Author: Pat Erley <pat-lkml@erley.org>
Date:   Wed Apr 21 06:23:19 2010 +0000

    This patch adds:
    
     ICH6 Southbridge,
     82915 Series Northbridge,
     P4 6xx Series CPU
    
    to inteltool
    
    Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630
    installed.
    
    Signed-off-by: Pat Erley <pat-lkml@erley.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27852aba6787617ca5656995cbc7e8ef0a3ea22c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 21 23:33:36 2010 +0000

    drop dead code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 04844816ac177254ce4128c1411041329050ac31
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 11:26:06 2010 +0000

    Inteltool: Add i830/Tolapai/Ich4 support
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8429de75a6cd6c6fbc13e0b85cbe9fba49dad211
Author: Loïc Grenié <loic.grenie@gmail.com>
Date:   Mon Nov 2 15:01:49 2009 +0000

    Add 82Q35/P35/Q33/G33/G31/P31 support to inteltool.
    The registers are (as far as I can tell) unchanged with respect to those
    of the PM965.
    
    Signed-off-by: Loïc Grenié <loic.grenie@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e23e37202cbad9dce81986efcd68e3a199db6605
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 30 17:14:24 2009 +0000

    Hm, quickfix to prevent the following crash, no idea yet what happens:
    
    *** glibc detected *** ././inteltool: double free or corruption (top): 0x08db0260 ***
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90d17407d8eeda82a6f4ba2170e97f609e8cc71b
Author: Maciej Pijanka <maciej.pijanka@gmail.com>
Date:   Wed Sep 30 17:05:46 2009 +0000

    Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB.
    
    Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7f2f258d8b44218c2efb83cfb276890fd4fb95c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 1 09:52:14 2009 +0000

    Clean up Mac OS X support of inteltool
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    Some minor modifications to allow 64bit/32bit compilation on Darwin
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2aedb1a3f2409b549c4094654281893b82c7435
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 29 15:45:43 2009 +0000

    add i810 and ich0
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9702b6bf7ec5a4fb16934f1cf2724480e2460c89
Author: Warren Turkal <wt@penguintechs.org>
Date:   Tue Jun 30 14:11:42 2009 +0000

    add new supported chipset
    Add identification for X58 and ICH10R.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f182456013a4416e176b000076b9f101c144d586
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 23:17:44 2009 +0000

    mini fix to reliably compile inteltool on darwin, and on Linux both on x86/x86_64.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1162f25a49e8f39822123d664cda10fef466b351
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Dec 4 15:18:20 2008 +0000

    Patch to util/inteltool:
    * PMBASE dumping now knows the registers.
    * Add support for i965, i975, ICH8M
    * Add support for Darwin OS using DirectIO
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d9a12f65df48bee260c522c1c2d32343cc7fd73
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 2 11:11:40 2008 +0000

    inteltool 82945G/GZ/P/PL Support (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2319027d7e3a9b44110794a553b10a554fed1102
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 20 13:41:24 2008 +0000

    split the one file, as the several printing functions will continue to grow
    immensly when they know more systems / cpus / chipsets
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb02f45e6ff2a6870353816712ff6271250dc7ee
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 20 12:42:39 2008 +0000

    use seperate array for core 2 cpus (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26ba091d5127315a651d7d165d76eb6f197f3198
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 18 10:58:09 2008 +0000

    inteltool: match cpuid before attempting to print MSRs (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b835974cd381b398ae0d5fbd6b7c789ebfd4e39
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jun 22 17:15:03 2008 +0000

    as per Peter's suggestion. clean binary in make clean
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 710e8b1ad0e01bea150cc66085176482b677cc19
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat May 17 21:33:35 2008 +0000

    Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial).
    
    Tested on hardware:
    Intel Northbridge: 8086:1a30 (i845)
    Intel Southbridge: 8086:2440 (ICH2)
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a6b6b51df7681931cea26c6e13d7a4fcd4650d3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 14 21:20:55 2008 +0000

    Cosmetics, whitespace, coding style, partially ident-aided (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9b99450ce759587c3702afc3271e89c137cee11
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 20:05:00 2008 +0000

    add ICH7-M and ICH7 DH to inteltool (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58a1cc1d3494daa1002bac617420373e097becee
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 14:47:32 2008 +0000

    fix license mentioning in manpage (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f7af6ef40e9ae2c535f9dc60b6bb53389242374
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 14:22:59 2008 +0000

    trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d466e6a8746c6dcdba8969618a3258093ae2392b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 13:52:50 2008 +0000

    trivial patch to fix options. Thanks to Uwe Hermann for the hint!
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b69e46bca3ee8e25ee45ba04ff812e507fccb0fc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 11:38:22 2008 +0000

    Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7
    have different register meanings, so they get their own lookup tables.
    
    This is a trivial patch.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03646bebbea8f2f4cace53be797dc727413ae69d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 13 22:14:21 2008 +0000

    Add new revised inteltool that dumps all kinds of chipset information and drop old
    gpio_dump utility.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
